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power management dec. 9, 2010 18v 2a step-down switching regulator SC4524D typical application circuit features wide input range: 3v to 18v 2a output current 200khz to 2mhz programmable frequency precision 1v feedback voltage peak current-mode control cycle-by-cycle current limiting hiccup overload protection with frequency foldback soft-start and enable thermal shutdown thermally enhanced 8-pin soic package fully rohs and weee compliant applications xdsl and cable modems set top boxes point of load applications cpe equipment dsp power supplies lcd and plasma tvs ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? description the SC4524D is a constant frequency peak current-mode step-down switching regulator capable of producing 2a output current from an input ranging from 3v to 18v. the switching frequency of the SC4524D is programmable up to 2mhz, allowing the use of small inductors and ceramic capacitors for miniaturization, and high input/ output conversion ratio. the SC4524D is suitable for next generation xdsl modems, high-defnition tvs and various point of load applications. peak current-mode pwm control employed in the SC4524D achieves fast transient response with simple loop compensation. cycle-by-cycle current limiting and hiccup overload protection reduces power dissipation during output overload. soft-start function reduces input start- up current and prevents the output from overshooting during power-up. the SC4524D is available in soic-8 edp package. figure 1. 1mhz 10v-16v to 5v/2a step-down converter efficiency 40 45 50 55 60 65 70 75 80 85 90 0 0.5 1 1.5 2 load current (a) efficiency (%) ss270 rev 4 v in = 12v SC4524D gnd in sw bst l1 6.8 p h c1 0.33 p f ss/en comp fb d2 20bq030 25.5k r6 102k 10nf c8 10pf c5 1nf l1: wurth 744 778 9006 out 5v/2a d1 1n4148 10v ? 16v rosc c2: murata grm31cr60j226k c4 2.2 p f c4: murata grm31cr61e225k v in c2 22 p f c7 r4 15.8k r5 30.1k r7
SC4524D 2 yyww=date code (example: 0752) xxxxx=semtech lot no. (example: e9010) pin confguration marking information ordering information device package SC4524Dsetrt (1)(2) soic-8 edp SC4524Devb evaluation board notes: (1) available in tape and reel only. a reel contains 2,500 devices. (2) available in lead-free package only. device is fully weee and rohs compliant and halogen-free. 1 2 3 4 bst sw 7 6 8 5 fb in comp rosc ss/en gnd 9 (8 - pin soic - edp)
SC4524D 3 exceeding the above specifcations may result in permanent damage to the device or device malfunction. operation outside of the parameters specifed in the electrical characteristics section is not recommended. notes- (1) calculated from package in still air, mounted to 3 x 4.5, 4 layer fr4 pcb with thermal vias under the exposed pad per jesd51 standards. (2) tested according to jedec standard jesd22-a114-b. electrical characteristics unless otherwise noted, v in = 12v, v bst = 15v, v ss = 2.2v, -40c < t j < 125c, r osc = 12.1k. absolute maximum ratings v in supply voltage -0.3 to 24v bst voltage 40v bst voltage above sw 36v ss voltage -0.3 to 3v fb voltage -0.3 to v in sw voltage -0.6 to v in sw transient spikes (10ns duration) -2.5v to v in +1.5v peak ir refow temperature . 260c esd protection level (2) 2000v thermal information junction to ambient (1) 36c/w junction to case (1) 5.5c/w maximum junction temperature 150c storage temperature -65 to +150c lead temperature (soldering) 10 sec 300c parameter conditions min typ max units input supply input voltage range 3 18 v v in start voltage v in rising 2.70 2.82 2.95 v v in start hysteresis 225 mv v in quiescent current v comp = 0 (not switching) 2 2.6 ma v in quiescent current in shutdown v ss/en = 0, v in = 12v 40 52 a error amplifer feedback voltage 0.980 1.000 1.020 v feedback voltage line regulation v in = 3v to 18v 0.005 %/v fb pin input bias current v fb = 1v, v comp = 0.8v -170 -340 na error amplifer transconductance 300 -1 error amplifer open-loop gain 60 db comp pin to switch current gain 10 a/v comp maximum voltage v fb = 0.9v 2.4 v comp source current v fb = 0.8v, v comp = 0.8v 17 a comp sink current v fb = 1.2v, v comp = 0.8v 25 internal power switch switch current limit (note 1) 2.6 3.3 4.3 a switch saturation voltage i sw = -2.6a 250 400 mv recommended operating conditions input voltage range 3v to 18v maximum output current 2a operating ambient temperature -40 to +105c operating junction temperature -40 to +125c
SC4524D 4 parameter conditions min typ max units minimum switch on-time 135 ns minimum switch of-time 100 ns switch leakage current 10 a minimum bootstrap voltage i sw = -2.6a 1.8 2.3 v bst pin current i sw = -2.6a 60 95 ma oscillator switching frequency r osc = 12.1k 1.04 1.3 1.56 mhz r osc = 73.2k 230 300 370 khz foldback frequency r osc = 12.1k, v fb = 0 100 250 khz r osc = 73.2k, v fb = 0 35 60 90 soft start and overload protection ss/en shutdown threshold 0.2 0.3 0.4 v ss/en switching threshold v fb = 0 v 0.95 1.2 1.4 v soft-start charging current v ss/en = 0 v 1.9 a v ss/en = 1.5 v 1.6 2.4 3.2 soft-start discharging current 1.5 a hiccup arming ss/en voltage v ss/en rising 2.15 v hiccup ss/en overload threshold v ss/en falling 1.9 v hiccup retry ss/en voltage v ss/en falling 0.6 1.0 1.2 v over temperature protection thermal shutdown temperature 165 c thermal shutdown hysteresis 10 c note 1: switch current limit does not vary with duty cycle. electrical characteristics (cont.) unless otherwise noted, v in = 12v , v bst = 15v, v ss = 2.2v, -40c < t j < 125c, r osc = 12.1k.
SC4524D 5 pin descriptions so-8 pin name pin function 1 sw emitter of the internal npn power transistor. connect this pin to the inductor, the freewheeling diode and the bootstrap capacitor. 2 in power supply to the regulator. it is also the collector of the internal npn power transistor. it must be closely by - passed to the ground plane. 3 rosc an external resistor from this pin to ground sets the oscillator frequency. 4 gnd ground pin 5 ss/en soft-start and regulator enable pin. a capacitor from this pin to ground provides soft-start and overload hiccup functions. hiccup can be disabled by overcoming the internal soft-start discharging current with an external pull- up resistor connected between the ss/en and the in pins. pulling the ss/en pin below 0.2v completely shuts of the regulator to low current state. 6 comp the output of the internal error amplifer. the voltage at this pin controls the peak switch current. a rc compensa - tion network at this pin stabilizes the regulator. 7 fb the inverting input of the error amplifer. if v fb falls below 0.8v, then the switching frequency will be reduced to improve short-circuit robustness (see applications information for details). 8 bst supply pin to the power transistor driver. tie to an external diode-capacitor bootstrap circuit to generate drive voltage higher than v in in order to fully enhance the internal npn power transistor. 9 exposed pad the exposed pad serves as a thermal contact to the circuit board. it is to be soldered to the ground plane of the pc board.
SC4524D 6 block diagram in 2 rosc 3 transistor r q s power slope comp + - isen ilim + - 18mv 5.5m + + bst reference & thermal shutdown 1v fault overload soft - start and overload hiccup control 1.9v r 8 sw 1 fb 7 ss/en 5 comp 6 oscillator clk ea pwm + - + 1.2v - frequency foldback gnd 4 + + - r oc pwm a1 v1 2 3 3 r s + - + - + + - r 8 sw 1 1 7 7 5 5 6 6 + - + - + - 4 + + - r pwm a1 v1 figure 2. SC4524D block diagram fault ss/en overload 1v/2.15v s q r + 2.4 p a 3.9 p a 1.9v - s r oc pwm q _ b1 b2 b3 b4 i c i d + - q _ i i figure 3. soft-start and overload hiccup control circuit
SC4524D 7 typical characteristics curve 1 efficiency 40 45 50 55 60 65 70 75 80 85 90 0 0.5 1 1.5 2 load current (a) efficiency (%) sc4524a/b v o =5v v o =3.3v v o =2.5v v o =1.5v 1mhz, v in =12v d 2 =20bq030 curve 7 switch saturation voltage vs switch current 50 100 150 200 250 300 0.0 0.5 1.0 1.5 2.0 2.5 switch current (a) v cesat (mv) ss270 rev 6-7 25 o c 125 o c -40 o c curve 4 frequency setting resistor vs frequency 1 10 100 1000 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 frequency (mhz) r osc (k ) ss270 rev 6-7 v in =12v curve 3 feedback voltage vs temperature 0.97 0.98 0.99 1.00 1.01 1.02 -50 -25 0 25 50 75 100 125 temperature ( o c) v fb (v) ss270 rev 6-7 v in =12v curve 9 bst pin current vs switch current 0.0 25.0 50.0 75.0 100.0 0 0.5 1 1.5 2 2.5 3 switch current (a) bst pin current (ma) ss270 rev 6-7 -40 o c 125 o c v in =12v v bst =15v curve 6 foldback frequency vs v fb 0 0.25 0.5 0.75 1 1.25 0.00 0.20 0.40 0.60 0.80 1.00 v fb (v) normalized frequency ss270 rev 6-7 r osc =73.2k r osc =12.1k t a =25 o c (2) efficiency 40 45 50 55 60 65 70 75 80 85 90 0 0.5 1 1.5 2 load current (a) efficiency (%) sc4524a/b v o =3.3v v o =2.5v v o =1.5v v o =1.0v 1mhz, v in =5v d 2 =20bq030 curve 8 switch current limit vs temperature 2.5 3.0 3.5 4.0 4.5 -50 -25 0 25 50 75 100 125 temperature ( o c) current limit (a) ss270 rev 6-7 curve 5 frequency vs temperature 0.8 0.9 1.0 1.1 1.2 -50 -25 0 25 50 75 100 125 temperature ( o c) normalized frequency ss270 rev 6-7 r osc =73.2k r osc =12.1k
SC4524D 8 typical characteristics (cont.) curve 10 v in thresholds vs temperature 2.4 2.5 2.6 2.7 2.8 2.9 3.0 -50 -25 0 25 50 75 100 125 temperature ( o c) v in threshold (v) ss270 rev 6-7 start uvlo curve 13 v in quiescent current vs v in 0.0 0.5 1.0 1.5 2.0 2.5 0 2 4 6 8 10 12 14 16 18 v in (v) current (ma) ss270 rev 6-7 v comp = 0 -40 o c 125 o c curve 12 v in shutdown current vs v in 0 10 20 30 40 50 0 2 4 6 8 10 12 14 16 18 v in (v) current (ua) ss270 rev 6-7 v ss = 0 -40 o c 125 o c curve 15 soft-start charging current vs soft-start voltage -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0 0.5 1 1.5 2 v ss (v) current (ua) ss270 rev 6-7 -40 o c 125 o c curve 11 v in supply current vs soft-start voltage 0.0 0.5 1.0 1.5 2.0 2.5 0 0.5 1 1.5 2 v ss (v) current (ma) ss270 rev 6-7 -40 o c 125 o c curve 14 ss shutdown threshold vs temperature 0.20 0.25 0.30 0.35 0.40 -50 -25 0 25 50 75 100 125 temperature ( o c) ss threshold (v) ss270 rev 6-7
SC4524D 9 applications information operation the SC4524D is a constant-frequency, peak current- mode, step-down switching regulator with an integrated 18v, 2.6a power npn transistor. programmable switching frequency makes the regulator design more fexible. with the peak current-mode control, the double reactive poles of the output lc flter are reduced to a single real pole by the inner current loop. this simplifes loop compensation and achieves fast transient response with a simple type-2 compensation network. as shown in figure 2, the switch collector current is sensed with an integrated 5.5m w sense resistor. the sensed current is summed with a slope-compensating ramp before it is compared with the transconductance error amplifer (ea) output. the pwm comparator trip point determines the switch turn-on pulse width. the current-limit comparator ilim turns of the power switch when the sensed signal exceeds the 18mv current-limit threshold. driving the base of the power transistor above the input power supply rail minimizes the power transistor saturation voltage and maximizes efciency. an external bootstrap circuit (formed by the capacitor c 1 and the diode d 1 in figure 1) generates such a voltage at the bst pin for driving the power transistor. shutdown and soft-start the ss/en pin is a multiple-function pin. an external capacitor (4.7nf to 22nf) connected from the ss pin to ground sets the soft-start and overload shutof times of the regulator (figure 3). the efect of v ss/en on the SC4524D is summarized in table 1. table 1: ss/en operation modes pulling the ss/en pin below 0.2v shuts of the regulator and reduces the input supply current to 18a (v in = 5v). ss/en mode supply current <0.2v shutdown 18ua @ 5vin 0.4v to 1.2v not switching 2ma 1.2v to 2.15v switching & hiccup disabled >2.15v switching & hiccup armed load dependent ss/en mode supply current <0.2v shutdown 18ua @ 5vin 0.4v to 1.2v not switching 2ma 1.2v to 2.15v switching & hiccup disabled >2.15v switching & hiccup armed load dependent when the ss/en pin is released, the soft-start capacitor is charged with an internal 1.9a current source (not shown in figure 3). as the ss/en voltage exceeds 0.4v, the internal bias circuit of the SC4524D turns on and the SC4524D draws 2ma from v in . the 1.9a charging current turns of and the 2.4a current source i c in figure 3 slowly charges the soft-start capacitor. the error amplifer ea in figure 2 has two non-inverting inputs. the non-inverting input with the lower voltage predominates. one of the non-inverting inputs is biased to a precision 1v reference and the other non-inverting input is tied to the output of the amplifer a 1 . amplifer a 1 produces an output v 1 = 2(v ss/en -1.2v). v 1 is zero and comp is forced low when v ss/en is below 1.2v. during start up, the efective non-inverting input of ea stays at zero until the soft-start capacitor is charged above 1.2v. once v ss/ en exceeds 1.2v, comp is released. the regulator starts to switch when v comp rises above 0.4v. if the soft-start interval is made sufciently long, then the fb voltage (hence the output voltage) will track v 1 during start up. v ss/en must be at least 1.83v for the output to achieve regulation. proper soft-start prevents output overshoot. current drawn from the input supply is also well controlled. overload / short-circuit protection table 2 lists various fault conditions and their corresponding protection schemes in the SC4524D. table 2: fault conditions and protections as summarized in table 1, overload shutdown is disabled during soft-start (v ss/en <2.15v). in figure 3, the reset input of the overload latch b 2 will remain high if the ss/en voltage is below 2.15v. once the soft-start capacitor is charged above 2.15v, the output of the schmitt trigger b 1 goes high, the reset input of b 2 goes low and hiccup condition fault protective action il>ilimit, v fb >0.8v over current cycle-by-cycle limit at programmed frequency il>ilimit, v fb <0.8v over current cycle-by-cycle limit with frequency foldback vss/en falling ss/en<1.9v persistent over current or short circuit shutdown, then retry (hiccup) tj>160c over temperature shutdown condition fault protective action il>ilimit, v fb >0.8v over current cycle-by-cycle limit at programmed frequency il>ilimit, v fb <0.8v over current cycle-by-cycle limit with frequency foldback vss/en falling ss/en<1.9v persistent over current or short circuit shutdown, then retry (hiccup) tj>160c over temperature shutdown
SC4524D 10 applications information (cont.) becomes armed. as the load draws more current from the regulator, the current-limit comparator ilim (figure 2) will eventually limit the switch current on a cycle-by- cycle basis. the over-current signal oc goes high, setting the latch b 3 . the soft-start capacitor is discharged with (i d - i c ) (figure 3). if the inductor current falls below the current limit and the pwm comparator instead turns of the switch, then latch b 3 will be reset and i c will recharge the soft-start capacitor. if over-current condition persists or oc becomes asserted more often than pwm over a period of time, then the soft-start capacitor will be discharged below 1.9v. at this juncture, comparator b 4 sets the overload latch b 2 . the soft-start capacitor will be continuously discharged with (i d - i c ). the comp pin is immediately pulled to ground. the switching regulator is shut of until the soft-start capacitor is discharged below 1.0v. at this moment, the overload latch is reset. the soft-start capacitor is recharged and the converter again undergoes soft-start. the regulator will go through soft- start, overload shutdown and restart until it is no longer overloaded. if the fb voltage falls below 0.8v because of output overload, then the switching frequency will be reduced. frequency foldback helps to limit the inductor current when the output is hard shorted to ground. during normal operation, the soft-start capacitor is charged to 2.4v. setting the output voltage the regulator output voltage is set with an external resistive divider (figure 1) with its center tap tied to the fb pin. for a given r 6 value, r 4 can be found by (1) setting the switching frequency the switching frequency of the SC4524D is set with an external resistor from the rosc pin to ground. table 3 lists standard resistor values for typical frequency setting. cesat d in d o v v v v v d ? + + = ? ? ? ? ? ? ? = 1 v 0 . 1 v r r o 6 4 1 sw d o l l f ) d 1 ( ) v v ( i ? ? ? + = d sw o d o 1 f i % 20 ) d 1 ( ) v v ( l ? ? ? ? + = ) d 1 ( d i i o cin _ rms ? ? ? = ? ? ? ? ? ? ? ? ? ? + ? d = d o sw l o c f 8 1 esr i v sw in o in f v 4 i c ? d ? > , r g r g s ca pwm ? ) / s q / s 1 ( ) / s 1 ( ) c r s 1 ( g v v 2 n 2 n p o esr pwm c o + + + + = 7 1 z 5 r f 2 1 c = 7 1 p 8 r f 2 1 c = , c r 1 o p , c r 1 o esr z = k 3 . 22 10 28 . 0 10 r 3 7 20 9 . 15 = ? = ? nf 45 . 0 10 1 . 22 10 16 2 1 c 3 3 5 = ? ? ? ? = pf 12 10 1 . 22 10 600 2 1 c 3 3 8 = ? ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? = o fb o c s ca c v v c f 2 1 r g 1 log 20 a db 9 . 15 3 . 3 0 . 1 10 22 10 80 2 1 10 1 . 6 28 1 log 20 a 6 3 3 c = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? ? m 7 g 10 r 20 c a = cesat d in d o v v v v v d ? + + = ? ? ? ? ? ? ? = 1 v 0 . 1 v r r o 6 4 1 sw d o l l f ) d 1 ( ) v v ( i ? ? ? + = d sw o d o 1 f i % 20 ) d 1 ( ) v v ( l ? ? ? ? + = ) d 1 ( d i i o cin _ rms ? ? ? = ? ? ? ? ? ? ? ? ? ? + ? d = d o sw l o c f 8 1 esr i v sw in o in f v 4 i c ? d ? > , r g r g s ca pwm ? ) / s q / s 1 ( ) / s 1 ( ) c r s 1 ( g v v 2 n 2 n p o esr pwm c o + + + + = 7 1 z 5 r f 2 1 c = 7 1 p 8 r f 2 1 c = , c r 1 o p , c r 1 o esr z = k 3 . 22 10 28 . 0 10 r 3 7 20 9 . 15 = ? = ? nf 45 . 0 10 1 . 22 10 16 2 1 c 3 3 5 = ? ? ? ? = pf 12 10 1 . 22 10 600 2 1 c 3 3 8 = ? ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? = o fb o c s ca c v v c f 2 1 r g 1 log 20 a db 9 . 15 3 . 3 0 . 1 10 22 10 80 2 1 10 1 . 6 28 1 log 20 a 6 3 3 c = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? ? m 7 g 10 r 20 c a = table 3: resistor for typical switching frequency minimum on time consideration the operating duty cycle of a non-synchronous step- down switching regulator in continuous-conduction mode (ccm) is given by (2) where v cesat is the switch saturation voltage and v d is voltage drop across the rectifying diode. in peak current-mode control, the pwm modulating ramp is the sensed current ramp of the power switch. this current ramp is absent unless the switch is turned on. the intersection of this ramp with the output of the voltage feedback error amplifer determines the switch pulse width. the propagation delay time required to immediately turn of the switch after it is turned on is the minimum controllable switch on time (t on(min) ). figure 4. variation of minimum on time with ambient temperature cesat d in d o v v v v v d ? + + = ? ? ? ? ? ? ? = 1 v 0 . 1 v r r o 6 4 1 sw d o l l f ) d 1 ( ) v v ( i ? ? ? + = d sw o d o 1 f i % 20 ) d 1 ( ) v v ( l ? ? ? ? + = ) d 1 ( d i i o cin _ rms ? ? ? = ? ? ? ? ? ? ? ? ? ? + ? d = d o sw l o c f 8 1 esr i v sw in o in f v 4 i c ? d ? > , r g r g s ca pwm ? ) / s q / s 1 ( ) / s 1 ( ) c r s 1 ( g v v 2 n 2 n p o esr pwm c o + + + + = 7 1 z 5 r f 2 1 c = 7 1 p 8 r f 2 1 c = , c r 1 o p , c r 1 o esr z = k 3 . 22 10 28 . 0 10 r 3 7 20 9 . 15 = ? = ? nf 45 . 0 10 1 . 22 10 16 2 1 c 3 3 5 = ? ? ? ? = pf 12 10 1 . 22 10 600 2 1 c 3 3 8 = ? ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? = o fb o c s ca c v v c f 2 1 r g 1 log 20 a db 9 . 15 3 . 3 0 . 1 10 22 10 80 2 1 10 1 . 6 28 1 log 20 a 6 3 3 c = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? ? m 7 g 10 r 20 c a = cesat d in d o v v v v v d ? + + = ? ? ? ? ? ? ? = 1 v 0 . 1 v r r o 6 4 1 sw d o l l f ) d 1 ( ) v v ( i ? ? ? + = d sw o d o 1 f i % 20 ) d 1 ( ) v v ( l ? ? ? ? + = ) d 1 ( d i i o cin _ rms ? ? ? = ? ? ? ? ? ? ? ? ? ? + ? d = d o sw l o c f 8 1 esr i v sw in o in f v 4 i c ? d ? > , r g r g s ca pwm ? ) / s q / s 1 ( ) / s 1 ( ) c r s 1 ( g v v 2 n 2 n p o esr pwm c o + + + + = 7 1 z 5 r f 2 1 c = 7 1 p 8 r f 2 1 c = , c r 1 o p , c r 1 o esr z = k 3 . 22 10 28 . 0 10 r 3 7 20 9 . 15 = ? = ? nf 45 . 0 10 1 . 22 10 16 2 1 c 3 3 5 = ? ? ? ? = pf 12 10 1 . 22 10 600 2 1 c 3 3 8 = ? ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? = o fb o c s ca c v v c f 2 1 r g 1 log 20 a db 9 . 15 3 . 3 0 . 1 10 22 10 80 2 1 10 1 . 6 28 1 log 20 a 6 3 3 c = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? ? m 7 g 10 r 20 c a = fig.4 minumum on time vs temperature 100 120 140 160 180 200 -50 -25 0 25 50 75 100 125 temperature ( o c) t on_min (ns) ss270 rev 6-7 v o =1.5v, i o =1a, 1mhz fig.4 minumum on time vs temperature 100 120 140 160 180 200 -50 -25 0 25 50 75 100 125 temperature ( o c) t on_min (ns) ss270 rev 6-7 v o =1.5v, i o =1a, 1mhz 5.23 2000 11.0 1300 30.9 600 5.62 1900 12.4 1200 38.3 500 6.34 1800 14.0 1100 49.9 400 7.15 1700 15.8 1000 57.6 350 8.06 1600 18.2 900 69.8 300 8.87 1500 21.5 800 84.5 250 9.76 1400 25.5 700 110 200 r osc (k) freq. (k) r osc (k) freq. (k) r osc (k) freq. (k)
SC4524D 11 applications information (cont.) closed-loop measurement shows that the SC4524D minimum on time is about 120ns at room temperature (figure 4). if the required switch on time is shorter than the minimum on time, the regulator will either skip cycles or it will jitter. to allow for transient headroom, the minimum operating switch on time should be at least 20% to 30% higher than the worst-case minimum on time. minimum of time limitation the pwm latch in figure 2 is reset every cycle by the clock. the clock also turns of the power transistor to refresh the bootstrap capacitor. this minimum of time limits the attainable duty cycle of the regulator at a given switching frequency. the measured minimum of time is 100ns typically. if the required duty cycle is higher than the attainable maximum, then the output voltage will not be able to reach its set value in continuous-conduction mode. inductor selection the inductor ripple current for a non-synchronous step- down converter in continuous-conduction mode is (3) where f sw is the switching frequency and l 1 is the inductance. an inductor ripple current between 20% to 50% of the maximum load current gives a good compromise among efciency, cost and size. re-arranging equation (3) and assuming 35% inductor ripple current, the inductor is given by (4) if the input voltage varies over a wide range, then choose l 1 based on the nominal input voltage. always verify converter operation at the input voltage extremes. the peak current limit of SC4524D power transistor is at cesat d in d o v v v v v d ? + + = ? ? ? ? ? ? ? = 1 v 0 . 1 v r r o 6 4 1 sw d o l l f ) d 1 ( ) v v ( i ? ? ? + = d sw o d o 1 f i % 20 ) d 1 ( ) v v ( l ? ? ? ? + = ) d 1 ( d i i o cin _ rms ? ? ? = ? ? ? ? ? ? ? ? ? ? + ? d = d o sw l o c f 8 1 esr i v sw in o in f v 4 i c ? d ? > , r g r g s ca pwm ? ) / s q / s 1 ( ) / s 1 ( ) c r s 1 ( g v v 2 n 2 n p o esr pwm c o + + + + = 7 1 z 5 r f 2 1 c = 7 1 p 8 r f 2 1 c = , c r 1 o p , c r 1 o esr z = k 3 . 22 10 28 . 0 10 r 3 7 20 9 . 15 = ? = ? nf 45 . 0 10 1 . 22 10 16 2 1 c 3 3 5 = ? ? ? ? = pf 12 10 1 . 22 10 600 2 1 c 3 3 8 = ? ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? = o fb o c s ca c v v c f 2 1 r g 1 log 20 a db 9 . 15 3 . 3 0 . 1 10 22 10 80 2 1 10 1 . 6 28 1 log 20 a 6 3 3 c = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? ? m 7 g 10 r 20 c a = cesat d in d o v v v v v d ? + + = ? ? ? ? ? ? ? = 1 v 0 . 1 v r r o 6 4 1 sw d o l l f ) d 1 ( ) v v ( i ? ? ? + = d sw o d o 1 f i % 20 ) d 1 ( ) v v ( l ? ? ? ? + = ) d 1 ( d i i o cin _ rms ? ? ? = ? ? ? ? ? ? ? ? ? ? + ? d = d o sw l o c f 8 1 esr i v sw in o in f v 4 i c ? d ? > , r g r g s ca pwm ? ) / s q / s 1 ( ) / s 1 ( ) c r s 1 ( g v v 2 n 2 n p o esr pwm c o + + + + = 7 1 z 5 r f 2 1 c = 7 1 p 8 r f 2 1 c = , c r 1 o p , c r 1 o esr z = k 3 . 22 10 28 . 0 10 r 3 7 20 9 . 15 = ? = ? nf 45 . 0 10 1 . 22 10 16 2 1 c 3 3 5 = ? ? ? ? = pf 12 10 1 . 22 10 600 2 1 c 3 3 8 = ? ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? = o fb o c s ca c v v c f 2 1 r g 1 log 20 a db 9 . 15 3 . 3 0 . 1 10 22 10 80 2 1 10 1 . 6 28 1 log 20 a 6 3 3 c = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? ? m 7 g 10 r 20 c a = cesat d in d o v v v v v d ? + + = ? ? ? ? ? ? ? = 1 v 0 . 1 v r r o 6 4 1 sw d o l l f ) d 1 ( ) v v ( i ? ? ? + = d ) d 1 ( d i i o cin _ rms ? ? ? = ? ? ? ? ? ? ? ? ? ? + ? d = d o sw l o c f 8 1 esr i v sw in o in f v 4 i c ? d ? > , r g r g s ca pwm ? ) / s q / s 1 ( ) / s 1 ( ) c r s 1 ( g v v 2 n 2 n p o esr pwm c o + + + + = 7 1 z 5 r f 2 1 c = 7 1 p 8 r f 2 1 c = , c r 1 o p , c r 1 o esr z = k 3 . 22 10 28 . 0 10 r 3 7 20 9 . 15 = ? = ? nf 45 . 0 10 1 . 22 10 16 2 1 c 3 3 5 = ? ? ? ? = pf 12 10 1 . 22 10 600 2 1 c 3 3 8 = ? ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? = o fb o c s ca c v v c f 2 1 r g 1 log 20 a db 9 . 15 3 . 3 0 . 1 10 22 10 80 2 1 10 1 . 6 28 1 log 20 a 6 3 3 c = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? ? m 7 g 10 r 20 c a = sw o d o 1 f i % 35 ) d 1 ( ) v v ( l ? ? ? ? + = cesat d in d o v v v v v d ? + + = ? ? ? ? ? ? ? = 1 v 0 . 1 v r r o 6 4 1 sw d o l l f ) d 1 ( ) v v ( i ? ? ? + = d ) d 1 ( d i i o cin _ rms ? ? ? = ? ? ? ? ? ? ? ? ? ? + ? d = d o sw l o c f 8 1 esr i v sw in o in f v 4 i c ? d ? > , r g r g s ca pwm ? ) / s q / s 1 ( ) / s 1 ( ) c r s 1 ( g v v 2 n 2 n p o esr pwm c o + + + + = 7 1 z 5 r f 2 1 c = 7 1 p 8 r f 2 1 c = , c r 1 o p , c r 1 o esr z = k 3 . 22 10 28 . 0 10 r 3 7 20 9 . 15 = ? = ? nf 45 . 0 10 1 . 22 10 16 2 1 c 3 3 5 = ? ? ? ? = pf 12 10 1 . 22 10 600 2 1 c 3 3 8 = ? ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? = o fb o c s ca c v v c f 2 1 r g 1 log 20 a db 9 . 15 3 . 3 0 . 1 10 22 10 80 2 1 10 1 . 6 28 1 log 20 a 6 3 3 c = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? ? m 7 g 10 r 20 c a = sw o d o 1 f i % 35 ) d 1 ( ) v v ( l ? ? ? ? + = least 2.6a. the maximum deliverable load current for the SC4524D is 2.6a minus one half of the inductor ripple current. input decoupling capacitor the input capacitor should be chosen to handle the rms ripple current of a buck converter. this value is given by (5) the input capacitance must also be high enough to keep input ripple voltage within specifcation. this is important in reducing the conductive emi from the regulator. the input capacitance can be estimated from (6) where d v in is the allowable input ripple voltage. multi-layer ceramic capacitors, which have very low esr (a few m w ) and can easily handle high rms ripple current, are the ideal choice for input fltering. a single 4.7f x5r ceramic capacitor is adequate for 500khz or higher switching frequency applications, and 10f is adequate for 200khz to 500khz switching frequency. for high voltage applications, a small ceramic (1f or 2.2f) can be placed in parallel with a low esr electrolytic capacitor to satisfy both the esr and bulk capacitance requirements. output capacitor the output ripple voltage d v o of a buck converter can be expressed as (7) where c o is the output capacitance. since the inductor ripple current d i l increases as d decreases (equation (3)), the output ripple voltage is therefore the highest when v in is at its maximum. a 10f to 47f x5r ceramic capacitor is found adequate for output fltering in most applications. ripple current in the output capacitor is not a concern because the cesat d in d o v v v v v d ? + + = ? ? ? ? ? ? ? = 1 v 0 . 1 v r r o 6 4 1 sw d o l l f ) d 1 ( ) v v ( i ? ? ? + = d sw o d o 1 f i % 20 ) d 1 ( ) v v ( l ? ? ? ? + = ) d 1 ( d i i o cin _ rms ? ? ? = ? ? ? ? ? ? ? ? ? ? + ? d = d o sw l o c f 8 1 esr i v sw in o in f v 4 i c ? d ? > , r g r g s ca pwm ? ) / s q / s 1 ( ) / s 1 ( ) c r s 1 ( g v v 2 n 2 n p o esr pwm c o + + + + = 7 1 z 5 r f 2 1 c = 7 1 p 8 r f 2 1 c = , c r 1 o p , c r 1 o esr z = k 3 . 22 10 28 . 0 10 r 3 7 20 9 . 15 = ? = ? nf 45 . 0 10 1 . 22 10 16 2 1 c 3 3 5 = ? ? ? ? = pf 12 10 1 . 22 10 600 2 1 c 3 3 8 = ? ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? = o fb o c s ca c v v c f 2 1 r g 1 log 20 a db 9 . 15 3 . 3 0 . 1 10 22 10 80 2 1 10 1 . 6 28 1 log 20 a 6 3 3 c = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? ? m 7 g 10 r 20 c a = cesat d in d o v v v v v d ? + + = ? ? ? ? ? ? ? = 1 v 0 . 1 v r r o 6 4 1 sw d o l l f ) d 1 ( ) v v ( i ? ? ? + = d sw o d o 1 f i % 20 ) d 1 ( ) v v ( l ? ? ? ? + = ) d 1 ( d i i o cin _ rms ? ? ? = ? ? ? ? ? ? ? ? ? ? + ? d = d o sw l o c f 8 1 esr i v sw in o in f v 4 i c ? d ? > , r g r g s ca pwm ? ) / s q / s 1 ( ) / s 1 ( ) c r s 1 ( g v v 2 n 2 n p o esr pwm c o + + + + = 7 1 z 5 r f 2 1 c = 7 1 p 8 r f 2 1 c = , c r 1 o p , c r 1 o esr z = k 3 . 22 10 28 . 0 10 r 3 7 20 9 . 15 = ? = ? nf 45 . 0 10 1 . 22 10 16 2 1 c 3 3 5 = ? ? ? ? = pf 12 10 1 . 22 10 600 2 1 c 3 3 8 = ? ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? = o fb o c s ca c v v c f 2 1 r g 1 log 20 a db 9 . 15 3 . 3 0 . 1 10 22 10 80 2 1 10 1 . 6 28 1 log 20 a 6 3 3 c = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? ? m 7 g 10 r 20 c a = cesat d in d o v v v v v d ? + + = ? ? ? ? ? ? ? = 1 v 0 . 1 v r r o 6 4 1 sw d o l l f ) d 1 ( ) v v ( i ? ? ? + = d sw o d o 1 f i % 20 ) d 1 ( ) v v ( l ? ? ? ? + = ) d 1 ( d i i o cin _ rms ? ? ? = ? ? ? ? ? ? ? ? ? ? + ? d = d o sw l o c f 8 1 esr i v sw in o in f v 4 i c ? d ? > , r g r g s ca pwm ? ) / s q / s 1 ( ) / s 1 ( ) c r s 1 ( g v v 2 n 2 n p o esr pwm c o + + + + = 7 1 z 5 r f 2 1 c = 7 1 p 8 r f 2 1 c = , c r 1 o p , c r 1 o esr z = k 3 . 22 10 28 . 0 10 r 3 7 20 9 . 15 = ? = ? nf 45 . 0 10 1 . 22 10 16 2 1 c 3 3 5 = ? ? ? ? = pf 12 10 1 . 22 10 600 2 1 c 3 3 8 = ? ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? = o fb o c s ca c v v c f 2 1 r g 1 log 20 a db 9 . 15 3 . 3 0 . 1 10 22 10 80 2 1 10 1 . 6 28 1 log 20 a 6 3 3 c = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? ? m 7 g 10 r 20 c a = cesat d in d o v v v v v d ? + + = ? ? ? ? ? ? ? = 1 v 0 . 1 v r r o 6 4 1 sw d o l l f ) d 1 ( ) v v ( i ? ? ? + = d sw o d o 1 f i % 20 ) d 1 ( ) v v ( l ? ? ? ? + = ) d 1 ( d i i o cin _ rms ? ? ? = ? ? ? ? ? ? ? ? ? ? + ? d = d o sw l o c f 8 1 esr i v sw in o in f v 4 i c ? d ? > , r g r g s ca pwm ? ) / s q / s 1 ( ) / s 1 ( ) c r s 1 ( g v v 2 n 2 n p o esr pwm c o + + + + = 7 1 z 5 r f 2 1 c = 7 1 p 8 r f 2 1 c = , c r 1 o p , c r 1 o esr z = k 3 . 22 10 28 . 0 10 r 3 7 20 9 . 15 = ? = ? nf 45 . 0 10 1 . 22 10 16 2 1 c 3 3 5 = ? ? ? ? = pf 12 10 1 . 22 10 600 2 1 c 3 3 8 = ? ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? = o fb o c s ca c v v c f 2 1 r g 1 log 20 a db 9 . 15 3 . 3 0 . 1 10 22 10 80 2 1 10 1 . 6 28 1 log 20 a 6 3 3 c = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? ? m 7 g 10 r 20 c a = cesat d in d o v v v v v d ? + + = ? ? ? ? ? ? ? = 1 v 0 . 1 v r r o 6 4 1 sw d o l l f ) d 1 ( ) v v ( i ? ? ? + = d sw o d o 1 f i % 20 ) d 1 ( ) v v ( l ? ? ? ? + = ) d 1 ( d i i o cin _ rms ? ? ? = ? ? ? ? ? ? ? ? ? ? + ? d = d o sw l o c f 8 1 esr i v sw in o in f v 4 i c ? d ? > , r g r g s ca pwm ? ) / s q / s 1 ( ) / s 1 ( ) c r s 1 ( g v v 2 n 2 n p o esr pwm c o + + + + = 7 1 z 5 r f 2 1 c = 7 1 p 8 r f 2 1 c = , c r 1 o p , c r 1 o esr z = k 3 . 22 10 28 . 0 10 r 3 7 20 9 . 15 = ? = ? nf 45 . 0 10 1 . 22 10 16 2 1 c 3 3 5 = ? ? ? ? = pf 12 10 1 . 22 10 600 2 1 c 3 3 8 = ? ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? = o fb o c s ca c v v c f 2 1 r g 1 log 20 a db 9 . 15 3 . 3 0 . 1 10 22 10 80 2 1 10 1 . 6 28 1 log 20 a 6 3 3 c = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? ? m 7 g 10 r 20 c a = cesat d in d o v v v v v d ? + + = ? ? ? ? ? ? ? = 1 v 0 . 1 v r r o 6 4 1 sw d o l l f ) d 1 ( ) v v ( i ? ? ? + = d sw o d o 1 f i % 20 ) d 1 ( ) v v ( l ? ? ? ? + = ) d 1 ( d i i o cin _ rms ? ? ? = ? ? ? ? ? ? ? ? ? ? + ? d = d o sw l o c f 8 1 esr i v sw in o in f v 4 i c ? d ? > , r g r g s ca pwm ? ) / s q / s 1 ( ) / s 1 ( ) c r s 1 ( g v v 2 n 2 n p o esr pwm c o + + + + = 7 1 z 5 r f 2 1 c = 7 1 p 8 r f 2 1 c = , c r 1 o p , c r 1 o esr z = k 3 . 22 10 28 . 0 10 r 3 7 20 9 . 15 = ? = ? nf 45 . 0 10 1 . 22 10 16 2 1 c 3 3 5 = ? ? ? ? = pf 12 10 1 . 22 10 600 2 1 c 3 3 8 = ? ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? = o fb o c s ca c v v c f 2 1 r g 1 log 20 a db 9 . 15 3 . 3 0 . 1 10 22 10 80 2 1 10 1 . 6 28 1 log 20 a 6 3 3 c = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? ? m 7 g 10 r 20 c a =
SC4524D 12 applications information (cont.) inductor current of a buck converter directly feeds c o , resulting in very low ripple current. avoid using z5u and y5v ceramic capacitors for output fltering because these types of capacitors have high temperature and high voltage coefcients. freewheeling diode use of schottky barrier diodes as freewheeling rectifers reduces diode reverse recovery input current spikes, easing high-side current sensing in the SC4524D. these diodes should have an average forward current rating at least 2a and a reverse blocking voltage of at least a few volts higher than the input voltage. for switching regulators operating at low duty cycles (i.e. low output voltage to input voltage conversion ratios), it is benefcial to use freewheeling diodes with somewhat higher average current ratings (thus lower forward voltages). this is because the diode conduction interval is much longer than that of the transistor. converter efciency will be improved if the voltage drop across the diode is lower. the freewheeling diode should be placed close to the sw pin of the SC4524D to minimize ringing due to trace inductance. 20bq030 (international rectifer), b230a (diodes inc.), ss13, ss23 (vishay), cmsh1-40m, cmsh1- 40ml and cmsh2-40m (central-semi.) are all suitable. the freewheeling diode should be placed close to the sw pin of the SC4524D on the pcb to minimize ringing due to trace inductance. bootstrapping the power transistor the typical minimum bst-sw voltage required to fully saturate the power transistor is shown in figure 5, which is about 1.96v at room temperature. the bst-sw voltage is supplied by a bootstrap circuit powered from either the input or the output of the converter (figure 6(a), 6(b) and 6(c)). to maximize efciency, tie the bootstrap diode to the converter output if v o >2.5v as shown in figure 6(a). since the bootstrap supply current is proportional to the converter load current, using a lower voltage to power the bootstrap circuit reduces driving loss and improves efciency. for the bootstrap circuit, a fast switching pn diode (such as 1n4148 or 1n914) and a small (0.33f C 0.47f) ceramic capacitor is sufcient for most applications. when bootstrapping from 2.5v to 3.0v output voltages, use a low forward drop schottky diode (bat-54 or similar) for d 1 . if vout > 8v, then a protection diode d4 between the sw and the bst pins will be required as shown in figure 6 (c). d4 can be a small pn diode such as 1n4148 or 1n914 if the operating temperature does not exceed 85 oc. use a small schottky diode (bat54 or similar) if the converter is to operate up to 125 oc. . figure 5. typical minimum bootstrap voltage required to saturate transistor (i sw = -2.6a). figure 6(a). bootstrapping the SC4524D from the converter output 12 12 fig.5 minimum bootstrap voltage vs temperature 1.6 1.7 1.8 1.9 2.0 2.1 2.2 -50 -25 0 25 50 75 100 125 temperature ( o c) voltage (v) ss270 rev 6-7 i sw = -2.6a 12 12 fig.5 minimum bootstrap voltage vs temperature 1.6 1.7 1.8 1.9 2.0 2.1 2.2 -50 -25 0 25 50 75 100 125 temperature ( o c) voltage (v) ss270 rev 6-7 i sw = -2.6a ( a ) sc 4524 d bst gnd in sw d 1 vout c 1 vin d 2 ( a )
SC4524D 13 applications information (cont.) figures 6(b) and 6(c). methods of bootstrapping the SC4524D loop compensation the goal of compensation is to shape the frequency response of the converter so as to achieve high dc accuracy and fast transient response while maintaining loop stability. figure 7. block diagram of control loops 12 12 fig.7 + - vo l1 co resr comp ea ref vc sw controller and schottky diode fb pwm modulator vramp ca r4 r6 c5 r7 c8 io rs 12 12 fig.7 + - vo l1 co resr comp ea ref vc sw controller and schottky diode fb pwm modulator vramp ca r4 r6 c5 r7 c8 io rs the block diagram in figure 7 shows the control loops of a buck converter with the SC4524D. the inner loop (current loop) consists of a current sensing resistor (r s =5.5m w ) and a current amplifer (ca) with gain (g ca =18.5). the outer loop (voltage loop) consists of an error amplifer (ea), a pwm modulator, and a lc flter. since the current loop is internally closed, the remaining task for the loop compensation is to design the voltage compensator (c 5 , r 7 , and c 8 ). for a converter with switching frequency f sw , output inductance l 1 , output capacitance c o and loading r, the control (v c ) to output (v o ) transfer function in figure 7 is given by: (8) this transfer function has a fnite dc gain an esr zero f z at a dominant low-frequency pole f p at and double poles at half the switching frequency. including the voltage divider (r 4 and r 6 ), the control to feedback transfer function is found and plotted in figure 8 as the converter gain. since the converter gain has only one dominant pole at low frequency, a simple type-2 compensation network is sufcient for voltage loop compensation. as shown in figure 8, the voltage compensator has a low frequency integrator pole, a zero at f z1 , and a high frequency pole at f p1 . the integrator is used to boost the gain at low frequency. the zero is introduced to compensate the excessive phase lag at the loop gain crossover due to the cesat d in d o v v v v v d ? + + = ? ? ? ? ? ? ? = 1 v 0 . 1 v r r o 6 4 1 sw d o l l f ) d 1 ( ) v v ( i ? ? ? + = d sw o d o 1 f i % 20 ) d 1 ( ) v v ( l ? ? ? ? + = ) d 1 ( d i i o cin _ rms ? ? ? = ? ? ? ? ? ? ? ? ? ? + ? d = d o sw l o c f 8 1 esr i v sw in o in f v 4 i c ? d ? > , r g r g s ca pwm ? ) / s q / s 1 ( ) / s 1 ( ) c r s 1 ( g v v 2 n 2 n p o esr pwm c o + + + + = 7 1 z 5 r f 2 1 c = 7 1 p 8 r f 2 1 c = , c r 1 o p , c r 1 o esr z = k 3 . 22 10 28 . 0 10 r 3 7 20 9 . 15 = ? = ? nf 45 . 0 10 1 . 22 10 16 2 1 c 3 3 5 = ? ? ? ? = pf 12 10 1 . 22 10 600 2 1 c 3 3 8 = ? ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? = o fb o c s ca c v v c f 2 1 r g 1 log 20 a db 9 . 15 3 . 3 0 . 1 10 22 10 80 2 1 10 1 . 6 28 1 log 20 a 6 3 3 c = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? ? m 7 g 10 r 20 c a = cesat d in d o v v v v v d ? + + = ? ? ? ? ? ? ? = 1 v 0 . 1 v r r o 6 4 1 sw d o l l f ) d 1 ( ) v v ( i ? ? ? + = d sw o d o 1 f i % 20 ) d 1 ( ) v v ( l ? ? ? ? + = ) d 1 ( d i i o cin _ rms ? ? ? = ? ? ? ? ? ? ? ? ? ? + ? d = d o sw l o c f 8 1 esr i v sw in o in f v 4 i c ? d ? > , r g r g s ca pwm ? ) / s q / s 1 ( ) / s 1 ( ) c r s 1 ( g v v 2 n 2 n p o esr pwm c o + + + + = 7 1 z 5 r f 2 1 c = 7 1 p 8 r f 2 1 c = , c r 1 o p , c r 1 o esr z = k 3 . 22 10 28 . 0 10 r 3 7 20 9 . 15 = ? = ? nf 45 . 0 10 1 . 22 10 16 2 1 c 3 3 5 = ? ? ? ? = pf 12 10 1 . 22 10 600 2 1 c 3 3 8 = ? ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? = o fb o c s ca c v v c f 2 1 r g 1 log 20 a db 9 . 15 3 . 3 0 . 1 10 22 10 80 2 1 10 1 . 6 28 1 log 20 a 6 3 3 c = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? ? m 7 g 10 r 20 c a = cesat d in d o v v v v v d ? + + = ? ? ? ? ? ? ? = 1 v 0 . 1 v r r o 6 4 1 sw d o l l f ) d 1 ( ) v v ( i ? ? ? + = d sw o d o 1 f i % 20 ) d 1 ( ) v v ( l ? ? ? ? + = ) d 1 ( d i i o cin _ rms ? ? ? = ? ? ? ? ? ? ? ? ? ? + ? d = d o sw l o c f 8 1 esr i v sw in o in f v 4 i c ? d ? > , r g r g s ca pwm ? ) / s q / s 1 ( ) / s 1 ( ) c r s 1 ( g v v 2 n 2 n p o esr pwm c o + + + + = 7 1 z 5 r f 2 1 c = 7 1 p 8 r f 2 1 c = , c r 1 o p , c r 1 o esr z = k 3 . 22 10 28 . 0 10 r 3 7 20 9 . 15 = ? = ? nf 45 . 0 10 1 . 22 10 16 2 1 c 3 3 5 = ? ? ? ? = pf 12 10 1 . 22 10 600 2 1 c 3 3 8 = ? ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? = o fb o c s ca c v v c f 2 1 r g 1 log 20 a db 9 . 15 3 . 3 0 . 1 10 22 10 80 2 1 10 1 . 6 28 1 log 20 a 6 3 3 c = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? ? m 7 g 10 r 20 c a = cesat d in d o v v v v v d ? + + = ? ? ? ? ? ? ? = 1 v 0 . 1 v r r o 6 4 1 sw d o l l f ) d 1 ( ) v v ( i ? ? ? + = d sw o d o 1 f i % 20 ) d 1 ( ) v v ( l ? ? ? ? + = ) d 1 ( d i i o cin _ rms ? ? ? = ? ? ? ? ? ? ? ? ? ? + ? d = d o sw l o c f 8 1 esr i v sw in o in f v 4 i c ? d ? > , r g r g s ca pwm ? ) / s q / s 1 ( ) / s 1 ( ) c r s 1 ( g v v 2 n 2 n p o esr pwm c o + + + + = 7 1 z 5 r f 2 1 c = 7 1 p 8 r f 2 1 c = , c r 1 o p , c r 1 o esr z = k 3 . 22 10 28 . 0 10 r 3 7 20 9 . 15 = ? = ? nf 45 . 0 10 1 . 22 10 16 2 1 c 3 3 5 = ? ? ? ? = pf 12 10 1 . 22 10 600 2 1 c 3 3 8 = ? ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? = o fb o c s ca c v v c f 2 1 r g 1 log 20 a db 9 . 15 3 . 3 0 . 1 10 22 10 80 2 1 10 1 . 6 28 1 log 20 a 6 3 3 c = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? ? m 7 g 10 r 20 c a = cesat d in d o v v v v v d ? + + = ? ? ? ? ? ? ? = 1 v 0 . 1 v r r o 6 4 1 sw d o l l f ) d 1 ( ) v v ( i ? ? ? + = d sw o d o 1 f i % 20 ) d 1 ( ) v v ( l ? ? ? ? + = ) d 1 ( d i i o cin _ rms ? ? ? = ? ? ? ? ? ? ? ? ? ? + ? d = d o sw l o c f 8 1 esr i v sw in o in f v 4 i c ? d ? > , r g r g s ca pwm ? ) / s q / s 1 ( ) / s 1 ( ) c r s 1 ( g v v 2 n 2 n p o esr pwm c o + + + + = 7 1 z 5 r f 2 1 c = 7 1 p 8 r f 2 1 c = , c r 1 o p , c r 1 o esr z = k 3 . 22 10 28 . 0 10 r 3 7 20 9 . 15 = ? = ? nf 45 . 0 10 1 . 22 10 16 2 1 c 3 3 5 = ? ? ? ? = pf 12 10 1 . 22 10 600 2 1 c 3 3 8 = ? ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? = o fb o c s ca c v v c f 2 1 r g 1 log 20 a db 9 . 15 3 . 3 0 . 1 10 22 10 80 2 1 10 1 . 6 28 1 log 20 a 6 3 3 c = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? ? m 7 g 10 r 20 c a = cesat d in d o v v v v v d ? + + = ? ? ? ? ? ? ? = 1 v 0 . 1 v r r o 6 4 1 sw d o l l f ) d 1 ( ) v v ( i ? ? ? + = d sw o d o 1 f i % 20 ) d 1 ( ) v v ( l ? ? ? ? + = ) d 1 ( d i i o cin _ rms ? ? ? = ? ? ? ? ? ? ? ? ? ? + ? d = d o sw l o c f 8 1 esr i v sw in o in f v 4 i c ? d ? > , r g r g s ca pwm ? ) / s q / s 1 ( ) / s 1 ( ) c r s 1 ( g v v 2 n 2 n p o esr pwm c o + + + + = 7 1 z 5 r f 2 1 c = 7 1 p 8 r f 2 1 c = , c r 1 o p , c r 1 o esr z = k 3 . 22 10 28 . 0 10 r 3 7 20 9 . 15 = ? = ? nf 45 . 0 10 1 . 22 10 16 2 1 c 3 3 5 = ? ? ? ? = pf 12 10 1 . 22 10 600 2 1 c 3 3 8 = ? ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? = o fb o c s ca c v v c f 2 1 r g 1 log 20 a db 9 . 15 3 . 3 0 . 1 10 22 10 80 2 1 10 1 . 6 28 1 log 20 a 6 3 3 c = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? ? m 7 g 10 r 20 c a = cesat d in d o v v v v v d ? + + = ? ? ? ? ? ? ? = 1 v 0 . 1 v r r o 6 4 1 sw d o l l f ) d 1 ( ) v v ( i ? ? ? + = d sw o d o 1 f i % 20 ) d 1 ( ) v v ( l ? ? ? ? + = ) d 1 ( d i i o cin _ rms ? ? ? = ? ? ? ? ? ? ? ? ? ? + ? d = d o sw l o c f 8 1 esr i v sw in o in f v 4 i c ? d ? > , r g r g s ca pwm ? ) / s q / s 1 ( ) / s 1 ( ) c r s 1 ( g v v 2 n 2 n p o esr pwm c o + + + + = 7 1 z 5 r f 2 1 c = 7 1 p 8 r f 2 1 c = , c r 1 o p , c r 1 o esr z = k 3 . 22 10 28 . 0 10 r 3 7 20 9 . 15 = ? = ? nf 45 . 0 10 1 . 22 10 16 2 1 c 3 3 5 = ? ? ? ? = pf 12 10 1 . 22 10 600 2 1 c 3 3 8 = ? ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? = o fb o c s ca c v v c f 2 1 r g 1 log 20 a db 9 . 15 3 . 3 0 . 1 10 22 10 80 2 1 10 1 . 6 28 1 log 20 a 6 3 3 c = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? ? m 7 g 10 r 20 c a = cesat d in d o v v v v v d ? + + = ? ? ? ? ? ? ? = 1 v 0 . 1 v r r o 6 4 1 sw d o l l f ) d 1 ( ) v v ( i ? ? ? + = d sw o d o 1 f i % 20 ) d 1 ( ) v v ( l ? ? ? ? + = ) d 1 ( d i i o cin _ rms ? ? ? = ? ? ? ? ? ? ? ? ? ? + ? d = d o sw l o c f 8 1 esr i v sw in o in f v 4 i c ? d ? > , r g r g s ca pwm ? ) / s q / s 1 ( ) / s 1 ( ) c r s 1 ( g v v 2 n 2 n p o esr pwm c o + + + + = 7 1 z 5 r f 2 1 c = 7 1 p 8 r f 2 1 c = , c r 1 o p , c r 1 o esr z = k 3 . 22 10 28 . 0 10 r 3 7 20 9 . 15 = ? = ? nf 45 . 0 10 1 . 22 10 16 2 1 c 3 3 5 = ? ? ? ? = pf 12 10 1 . 22 10 600 2 1 c 3 3 8 = ? ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? = o fb o c s ca c v v c f 2 1 r g 1 log 20 a db 9 . 15 3 . 3 0 . 1 10 22 10 80 2 1 10 1 . 6 28 1 log 20 a 6 3 3 c = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? ? m 7 g 10 r 20 c a = d 1 d 1 ( b ) ( b ) sc 4524 d bst gnd in sw vout c 1 vin d 2 d 2 d 1 ( c ) sc 4524 d bst gnd in sw vout > 8 v c 1 vin d 2 d 4 d 4 is either a pn juntion diode or a schottky diode depending on the operating temperature .
SC4524D 14 applications information (cont.) integrator pole (-90deg) and the dominant pole (-90deg). the high frequency pole nulls the esr zero and attenuates high frequency noise. figure 8. bode plots for voltage loop design therefore, the procedure of the voltage loop design for the SC4524D can be summarized as: (1) plot the converter gain, i.e. control to feedback transfer function. (2) select the open loop crossover frequency, f c , between 10% and 20% of the switching frequency. at f c , fnd the required compensator gain, a c . in typical applications with ceramic output capacitors, the esr zero is neglected and the required compensator gain at f c can be estimated by (9) (3) place the compensator zero, f z1 , between 10% and 20% of the crossover frequency, f c . (4) use the compensator pole, f p1 , to cancel the esr zero, f z . (5) then, the parameters of the compensation network can be calculated by fig.8 fp fsw/2 fz1 fp1 fc fz 1k 10k 100k 1m 10m -60 -30 0 30 60 gain (db) frequency (hz) c o n v e rt e r g a i n l o o p g a i n c o m p e ns a t o r g a i n fig.8 fp fsw/2 fz1 fp1 fc fz 1k 10k 100k 1m 10m -60 -30 0 30 60 gain (db) frequency (hz) c o n v e rt e r g a i n l o o p g a i n c o m p e ns a t o r g a i n cesat d in d o v v v v v d ? + + = ? ? ? ? ? ? ? = 1 v 0 . 1 v r r o 6 4 1 sw d o l l f ) d 1 ( ) v v ( i ? ? ? + = d sw o d o 1 f i % 20 ) d 1 ( ) v v ( l ? ? ? ? + = ) d 1 ( d i i o cin _ rms ? ? ? = ? ? ? ? ? ? ? ? ? ? + ? d = d o sw l o c f 8 1 esr i v sw in o in f v 4 i c ? d ? > , r g r g s ca pwm ? ) / s q / s 1 ( ) / s 1 ( ) c r s 1 ( g v v 2 n 2 n p o esr pwm c o + + + + = 7 1 z 5 r f 2 1 c = 7 1 p 8 r f 2 1 c = , c r 1 o p , c r 1 o esr z = k 3 . 22 10 28 . 0 10 r 3 7 20 9 . 15 = ? = ? nf 45 . 0 10 1 . 22 10 16 2 1 c 3 3 5 = ? ? ? ? = pf 12 10 1 . 22 10 600 2 1 c 3 3 8 = ? ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? = o fb o c s ca c v v c f 2 1 r g 1 log 20 a db 9 . 15 3 . 3 0 . 1 10 22 10 80 2 1 10 1 . 6 28 1 log 20 a 6 3 3 c = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? ? m 7 g 10 r 20 c a = cesat d in d o v v v v v d ? + + = ? ? ? ? ? ? ? = 1 v 0 . 1 v r r o 6 4 1 sw d o l l f ) d 1 ( ) v v ( i ? ? ? + = d sw o d o 1 f i % 20 ) d 1 ( ) v v ( l ? ? ? ? + = ) d 1 ( d i i o cin _ rms ? ? ? = ? ? ? ? ? ? ? ? ? ? + ? d = d o sw l o c f 8 1 esr i v sw in o in f v 4 i c ? d ? > , r g r g s ca pwm ? ) / s q / s 1 ( ) / s 1 ( ) c r s 1 ( g v v 2 n 2 n p o esr pwm c o + + + + = 7 1 z 5 r f 2 1 c = 7 1 p 8 r f 2 1 c = , c r 1 o p , c r 1 o esr z = k 3 . 22 10 28 . 0 10 r 3 7 20 9 . 15 = ? = ? nf 45 . 0 10 1 . 22 10 16 2 1 c 3 3 5 = ? ? ? ? = pf 12 10 1 . 22 10 600 2 1 c 3 3 8 = ? ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? = o fb o c s ca c v v c f 2 1 r g 1 log 20 a db 9 . 15 3 . 3 0 . 1 10 22 10 80 2 1 10 1 . 6 28 1 log 20 a 6 3 3 c = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? ? m 7 g 10 r 20 c a = where g m =0.3ma/v is the ea gain of the SC4524D. example : determine the voltage compensator for an 800khz, 12v to 3.3v/2a converter with 22uf ceramic output capacitor. choose a loop gain crossover frequency of 80khz, and place voltage compensator zero and pole at f z1 =16khz (20% of f c ), and f p1 =600khz. from equation (9), the required compensator gain at f c is then the compensator parameters are select r 7 =12.4k, c 5 =1nf, and c 8 =22pf for the design. compensator parameters for various typical applications are listed in table 5. a mathcad program is also available upon request for detailed calculation of the compensator parameters. thermal considerations for the power transistor inside the SC4524D, the conduction loss p c , the switching loss p sw , and bootstrap circuit loss p bst, can be estimated as follows: (10) where v bst is the bst supply voltage and t s is the equivalent 11.4db 3.3 1.0 10 22 10 80 2 ? 1 10 5.5 18.5 1 log 20 a 6 3 3 c ? ? 1 ? ? ? ? ? ? ? ? ? ? 11.4db 3.3 1.0 10 22 10 80 2 ? 1 10 5.5 18.5 1 log 20 a 6 3 3 c ? ? 1 ? ? ? ? ? ? ? ? ? ? k 4 . 2 1 10 0.3 10 r 3 7 20 11.4 ? 0.8nf 10 4 . 2 1 10 16 2 ? 1 c 3 3 5 ? ? ? ? pf 1 2 10 4 . 2 1 10 600 ? 2 1 c 3 3 8 ? ? ? ? k 4 . 2 1 10 0.3 10 r 3 7 20 11.4 ? 0.8nf 10 4 . 2 1 10 16 2 ? 1 c 3 3 5 ? ? ? ? pf 1 2 10 4 . 2 1 10 600 ? 2 1 c 3 3 8 ? ? ? ? o cesat c i v d p ? ? = 40 i v d p o bst bst ? ? = dc 2 o ind r i ) 3 . 1 ~ 1 . 1 ( p ? ? = o d d i v ) d 1 ( p ? ? ? = sw o in s sw f i v t 2 1 p ? ? ? ? = q bst sw c total p p p p p + + + = ma 2 v p in q ? = o cesat c i v d p ? ? = 40 i v d p o bst bst ? ? = dc 2 o ind r i ) 3 . 1 ~ 1 . 1 ( p ? ? = o d d i v ) d 1 ( p ? ? ? = sw o in s sw f i v t 2 1 p ? ? ? ? = q bst sw c total p p p p p + + + = ma 2 v p in q ? = cesat d in d o v v v v v d ? + + = ? ? ? ? ? ? ? = 1 v 0 . 1 v r r o 6 4 1 sw d o l l f ) d 1 ( ) v v ( i ? ? ? + = d sw o d o 1 f i % 20 ) d 1 ( ) v v ( l ? ? ? ? + = ) d 1 ( d i i o cin _ rms ? ? ? = ? ? ? ? ? ? ? ? ? ? + ? d = d o sw l o c f 8 1 esr i v sw in o in f v 4 i c ? d ? > , r g r g s ca pwm ? ) / s q / s 1 ( ) / s 1 ( ) c r s 1 ( g v v 2 n 2 n p o esr pwm c o + + + + = 7 1 z 5 r f 2 1 c = 7 1 p 8 r f 2 1 c = , c r 1 o p , c r 1 o esr z = k 3 . 22 10 28 . 0 10 r 3 7 20 9 . 15 = ? = ? nf 45 . 0 10 1 . 22 10 16 2 1 c 3 3 5 = ? ? ? ? = pf 12 10 1 . 22 10 600 2 1 c 3 3 8 = ? ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? = o fb o c s ca c v v c f 2 1 r g 1 log 20 a db 9 . 15 3 . 3 0 . 1 10 22 10 80 2 1 10 1 . 6 28 1 log 20 a 6 3 3 c = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? ? m 7 g 10 r 20 c a =
SC4524D 15 switching time of the npn transistor (see table 4). table 4. typical switching time in addition, the quiescent current loss is (11) the total power loss of the SC4524D is therefore (12) the temperature rise of the SC4524D is the product of the total power dissipation (equation (12)) and q ja (36 o c/w), which is the thermal impedance from junction to ambient for the soic-8 edp package. it is not recommended to operate the SC4524D above 125 o c junction temperature. in the applications with high input voltage and high output current, the switching frequency may need to be reduced to meet the thermal requirement. o cesat c i v d p ? ? = 40 i v d p o bst bst ? ? = dc 2 o ind r i ) 3 . 1 ~ 1 . 1 ( p ? ? = o d d i v ) d 1 ( p ? ? ? = sw o in s sw f i v t 2 1 p ? ? ? ? = q bst sw c total p p p p p + + + = ma 2 v p in q ? = o cesat c i v d p ? ? = 40 i v d p o bst bst ? ? = dc 2 o ind r i ) 3 . 1 ~ 1 . 1 ( p ? ? = o d d i v ) d 1 ( p ? ? ? = sw o in s sw f i v t 2 1 p ? ? ? ? = q bst sw c total p p p p p + + + = ma 2 v p in q ? = o cesat c i v d p ? ? = 40 i v d p o bst bst ? ? = dc 2 o ind r i ) 3 . 1 ~ 1 . 1 ( p ? ? = o d d i v ) d 1 ( p ? ? ? = sw o in s sw f i v t 2 1 p ? ? ? ? = q bst sw c total p p p p p + + + = ma 2 v p in q ? = o cesat c i v d p ? ? = 40 i v d p o bst bst ? ? = dc 2 o ind r i ) 3 . 1 ~ 1 . 1 ( p ? ? = o d d i v ) d 1 ( p ? ? ? = sw o in s sw f i v t 2 1 p ? ? ? ? = q bst sw c total p p p p p + + + = ma 2 v p in q ? = pcb layout considerations in a step-down switching regulator, the input bypass capacitor, the main power switch and the freewheeling diode carry pulse current (figure 9). for jitter-free operation, the size of the loop formed by these components should be minimized. since the power switch is already integrated within the SC4524D, connecting the anode of the freewheeling diode close to the negative terminal of the input bypass capacitor minimizes size of the switched current loop. the input bypass capacitor should be placed close to the in pin. shortening the traces of the sw and bst nodes reduces the parasitic trace inductance at these nodes. this not only reduces emi but also decreases switching voltage spikes at these nodes. the exposed pad should be soldered to a large ground plane as the ground copper acts as a heat sink for the device. to ensure proper adhesion to the ground plane, avoid using vias directly under the device. figure 9. heavy lines indicate the critical pulse current loop. the stray inductance of this loop should be minimized. 12 12 fig.9 vout vin + + curre nts in power section in v out v l z 1a 2a 12v 12.5ns 15.3ns input voltage load current
SC4524D 16 recommended component parameters in typical applications table 5 lists the recommended inductance (l 1 ) and compensation network (r 7 , c 5 , c 8 ) for common input and output voltages. the inductance is determined by assuming that the ripple current is 35% of load current i o . the compensator parameters are calculated by assuming a 22 m f low esr ceramic output capacitor and a loop gain crossover frequency of f sw /10. table 5. recommended inductance (l 1 ) and compensator (r 7 , c 5 , c 8 ) typical application s recommended parameters vin (v) vo (v) io (a) fsw (khz) c2 (uf) l1 (uh) r7 (k) c5 (nf) c8 (pf) 500 6.8 4.02 3.3 1000 3.3 7.5 0.82 500 3.3 4.02 3.3 1000 1.5 7.5 0.82 500 4.7 13.3 0.82 1000 2.2 21.5 0.68 500 2.2 11 0.82 1000 1.5 21.5 0.68 500 6.8 4.02 3.3 1000 3.3 7.68 0.82 500 3.3 4.02 3.3 1000 2.2 7.68 0.82 500 8.2 6.81 2.2 1000 4.7 14.3 0.68 500 4.7 6.81 1.5 1000 2.2 12.1 0.68 500 6.8 9.09 1 1000 3.3 16.2 0.68 500 3.3 9.09 1 1000 2.2 17.8 0.68 1 500 8.2 4.32 3.3 2 500 4.7 4.32 3.3 22 500 15 6.81 1.5 22 1000 6.8 12.1 0.82 10 500 6.8 6.81 1.5 22 1000 3.3 12.1 0.68 10 500 15 9.09 1 22 1000 8.2 18.7 0.68 10 500 8.2 9.09 1 22 1000 4.7 18.7 0.68 500 15 14.3 0.82 1000 10 24.9 0.68 500 8.2 14.3 0.82 1000 4.7 27.4 0.68 500 15 21.5 0.82 1000 8.2 38.3 0.68 500 8.2 21.5 0.82 1000 4.7 38.3 0.68 500 10 25.5 0.82 1000 4.7 51.1 0.68 500 4.7 25.5 0.82 1000 2.2 51.1 0.68 10 3.3 5 12 1.5 2.5 1.5 2.5 3.3 1.5 2.5 3.3 5 7.5 10 1 2 1 1 2 1 1 1 1 2 2 2 2 2 2 22 10 1 1 1 2 2
SC4524D 17 typical application schematics SC4524D gnd in sw bst l1 2.2 p h c1 0.33 p f ss/en comp fb d2 20bq030 14.3k r6 33.2k 10nf c8 10pf c5 0.68nf l1: coiltronics ld1-2r2 out 3.3v/2a d1 1n4148 5v rosc c2: murata grm31cr60j226k c4 4.7 p f c4: murata grm31cr60j475k v in c2 22 p f c7 r4 15.8k r5 17.8k r7 figure 10. 1mhz 5v to 3.3v/2a step-down converter fig 11: 500khz 10v-16v to 1.5v/2a step-down converter SC4524D gnd in sw bst l1 4.7 p h c1 0.33 p f ss/en comp fb d2 20bq030 66.5k r6 33.2k 10nf c8 33pf c5 3.3nf l1: coiltronics dr73-4r7 out 1.5v/2a d1 1n4148 10v ? 16v rosc c2: murata grm31cr60j226k c4 4.7 p f c4: murata grm31cr60j475k v in c2 22 p f c7 r4 38.3k r5 4.32k r7 figure 11. 500khz 10v-16v to 1.5v/2a step-down converter
SC4524D 18 lc load characteristic 0 1 2 3 4 5 6 0 0.5 1 1.5 2 2.5 3 load current (a) output voltage (v) ss270 rev 6-7 figure 12(a). load characteristic ss 12v input (5v/div) 5v output (2v/div) 10ms/div ss voltage (1v/div) figure 12(b). v in start up transient (i o =2a) figure 12(c). load transient response (i o = 0.3a to 2a) figure 12(d). output short circuit (hiccup) tr 5v output response (500mv/div, ac coupling) inductor current (1a/div) 40us/div ocp 5v output short (5v/div) retry inductor current (2a/div) 20ms/div ss voltage (2v/div) typical performance characteristics (for a 12v to 5v/2a step-down converter with 1mhz switching frequency)
SC4524D 19 outline drawing - soic-8 edp see detail detail a a . 050 bsc . 236 bsc 8 . 010 . 150 . 189 . 154 . 193 . 012 - 8 0 . 25 1 . 27 bsc 6 . 00 bsc 3 . 90 4 . 90 - . 157 . 197 3 . 80 4 . 80 . 020 0 . 31 4 . 00 5 . 00 0 . 51 bxn 2 x n / 2 tips seating aaa c e / 2 2 x 1 2 n a d a 1 e 1 bbb c a - b d ccc c e / 2 e a 2 (. 041 ) . 004 . 008 - . 028 - - - - 0 . 016 . 007 . 049 . 000 . 053 8 0 0 . 20 0 . 10 - 8 0 . 40 0 . 17 1 . 25 0 . 00 . 041 . 010 . 069 . 065 . 005 1 . 35 ( 1 . 05 ) 0 . 72 - 1 . 04 0 . 25 - - - 1 . 75 1 . 65 0 . 13 0 . 25 - . 010 . 020 0 . 50 - c l ( l 1 ) 01 0 . 25 gage plane h 3 . dimensions " e 1 " and " d " do not include mold flash , protrusions or gate burrs . - b - controlling dimensions are in millimeters ( angles in degrees ). datums and to be determined at datum plane notes : 1 . 2 . - a - - h - side view a b c d e h plane exposed pad l 1 n 01 bbb aaa ccc a b a 2 a 1 d e e 1 l h e c dim min millimeters nom dimensions inches min max max nom f h h f h . 085 . 120 . 095 . 116 . 130 . 099 2 . 95 2 . 15 3 . 05 2 . 41 3 . 30 2 . 51 4 . reference jedec std ms - 012 , variation ba .
SC4524D 20 land pattern - soic-8 edp this land pattern is for reference purposes only . consult your manufacturing group to ensure your company ' s manufacturing guidelines are met . notes : 1 . reference ipc - sm - 782 a , rlp no . 300 a . 2 . 3 . thermal vias in the land pattern of the exposed pad shall be connected to a system ground plane . failure to do so may compromise the thermal and / or functional performance of the device . e z ( c ) g p ? 0 . 36 mm thermal via x y solder mask ( 5 . 20 ) c (. 205 ) x y z f g p d e . 024 . 087 . 291 . 101 . 118 . 050 . 201 . 134 0 . 60 2 . 20 7 . 40 2 . 56 3 . 00 1 . 27 5 . 10 3 . 40 millimeters inches dim dimensions d f
contact information semtech corporation power mangement products division 200 flynn road, camarillo, ca 93012 phone: (805) 498-2111 fax: (805) 498-3804 SC4524D 21 ? semtech 2010 all rights reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. semtech assumes no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specifed maximum ratings or operation outside the specifed range. semtech products are not designed, intended, authorized or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. inclusion of semtech products in such ap - plications is understood to be undertaken solely at the customers own risk. should a customer purchase or use semtech products for any such unauthorized application, the customer shall indemnify and hold semtech and its ofcers, em - ployees, subsidiaries, afliates, and distributors harmless against all claims, costs damages and attorney fees which could arise.

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